The fitness function works in two stages. The validity of the circuit outputs or the functional output is taken into account in the initial stage. GA uses to optimize the number of transistor count after the functional solution appeared. This research is mainly focused on the optimization of transistor used in the digital circuit but not the number of gate. In this study, we proposed a method to design the structure of the combination logic circuit using EA. This approach is able to optimize the usage of logic gate compare to the conventional method.
The main objective of this research is to design a digital circuit which can produce the desired output function with the most minimum usage of logic gates. The structure of the digital circuit is encoded into one-dimensional genotype as represented by a finite string of bits. The design process then be done by the Genetic Algorithm GA operator such as crossover, mutation and selection. The best solution found is decoded back to the digital circuit structure. In this study a selected optimization method is based on a genetic algorithm.
Genetic Algorithm s GA are adaptive heuristic search algorithm premised on the evolutionary ideal of natural selection and genetic. The basic concept of GA is designed to simulate processes in natural system necessary for evolution, specifically those that follow the principles first laid down by Darwin of survival of the fittest.
The GA works by creating many random solutions to the problem at hand. This solutions will be subjected to an imitation of the evolution of species. All these solution are coded as genetic chromosomes and it will be made to mate by hybridization, also throwing in the occasional spontaneous mutation.
The offspring generated will include some solutions that are better than the original. The proposed approach represented the solution inside the block in Fig. The detail solutions inside the block are encoded into a string of chromosomes and subjected to the process of evolutionary algorithms. The architecture of the proposed system is shown in Fig. We use an encoding system to represent the structure of combination logic circuit. The two-dimension phenotype is encoded into one-dimension genotype as represented by a finite string of bits.
Every logic gate has two inputs and one output. The structures of gates are arranged in G x,y matrix form which x is represented the gate in row and y is represented the gate in the column. The m inputs is connected to y column of the logic gates. The possible input combination is based on 2 m. The system process is started with the random generation of initial population.
The length of the chromosomes is depend on the size of the entire structure. The number of bit in the chromosomes represents type of gate. The collection of all individuals of the cell represents a solution. The design has fitness of 1 if it output value satisfies the constraint specification. Otherwise the structure design is deviated from the performance specification. The structure design modification is done by crossover and mutation operator.
Crossover is the technique of exploring new regions of the search space to produce design other than the random population which generated in the initial stage. Crossover is a randomized approach to exchange information between two chromosomes. The new population is produced by crossover. The process of crossover can creates new structures from the existing structures.
Crossover operation creates a variation in the population by producing offerings that combine characteristics from the two parents but are different from either of the parents. Mutation is an approach to prevent the solutions in the population falling into a local optimum of the solved problem. Mutation operation randomly changes the offspring resulted from crossover. The fitness of the process is the correctness of the obtained logic circuit in matching the truth table of the required function.
In this study, we proposed a fitness functional called constraint fitness.
The constraint fitness is based on the comparison of circuit output with the constraint output. The formula for Constraint Fitness CF is:. F C is achieved 1 when x is equal to 1. Consequently, F C will equal to 1 due to x is 1. It is possible to get more that one constraint fitness in a random generated population. In order to determine the global optimum of the design, we accumulated all the population with the constraint fitness equal to 1 for further evaluation.
In this research, we are targeting the optimization of number of gates used in the structure design. After obtained the constraint fitness, the second objective is to get the fitness of gate optimization used in the circuit design. The population for this Gate Optimization Fitness GOF evaluation is base on the chromosome with the constraint fitness of 1.
Each string of chromosome is evaluated for the gate optimization fitness. The algorithm for this fitness is:. The numerator of  is the summation of the gates which can produces the constraint fitness equal to 1. The denominator part is the summation of the gate per structure. The fitness of GOF should in between 0 and 1. The global optimal is achieved when met the smaller fitness of GOF. Experiments have been conducted using the system to investigate its effectiveness in constraint-directed logic synthesis.
The results produced by the proposed approach were compared with those generated by K-Map method. Combination logic gates boolean function of the designs are illustrated in the different table. These results show that the proposed system is able to produce quite effective solution of constraint-directed logic synthesis. Table 2 shows the first example result. Convergence to the optimum was achieved in generation Figure 3 shows the digital circuit schematic for Example 1 which was designed by the proposed method.
Meanwhile, the solution for Example 1 that designed by convention K-Map method is illustrated in Fig. Obviously, the circuit designed by the proposed method needs lesser gate if compared to the conventional method. Table 3 shows the second example results. The proposed approach produces less number of gate counts by For example 2, the digital circuit schematics of both designs are shown in Fig. Clearly, the circuit design implemented by the proposed method requires smaller number of gate if compared to the conventional design.
Each CF achieved value of 1 in different population.
The lowest GOF for Example 1 is 0. The solutions show that the proposed method is able to optimize the gate count in the digital circuit design.
Special attention must be given to the sizing of the transistors in dynamic circuits to make them immune to noise. Digital sequential logic circuits are divided into synchronous and asynchronous types. Sequential systems divide into two further subcategories. Buy eBook. This means that many such serial chains of cells must provide their outputs before the expiration of an interval of time.
The advantages of the proposed method are as follows:. The obtained results for the digital circuit structure are based on the gate count instead of transistor count, area, delay and power consumption. Therefore, the results are bench marking with the conventional design method. The state of a synchronous circuit only changes on clock pulses.
At each cycle, the next state is determined by the current state and the value of the input signals when the clock pulse occurs. The main advantage of synchronous logic is its simplicity. The logic gates which perform the operations on the data require a finite amount of time to respond to changes to their inputs. This is called propagation delay. The interval between clock pulses must be long enough so that all the logic gates have time to respond to the changes and their outputs "settle" to stable logic values, before the next clock pulse occurs.
As long as this condition is met ignoring certain other details the circuit is guaranteed to be stable and reliable. This determines the maximum operating speed of a synchronous circuit. Asynchronous sequential logic is not synchronized by a clock signal; the outputs of the circuit change directly in response to changes in inputs. The advantage of asynchronous logic is that it can be faster than synchronous logic, because the circuit doesn't have to wait for a clock signal to process inputs.
The speed of the device is potentially limited only by the propagation delays of the logic gates used. However, asynchronous logic is more difficult to design and is subject to problems not encountered in synchronous designs. The main problem is that digital memory elements are sensitive to the order that their input signals arrive; if two signals arrive at a flip-flop or latch at almost the same time, which state the circuit goes into can depend on which signal gets to the gate first.
Therefore, the circuit can go into the wrong state, depending on small differences in the propagation delays of the logic gates. This is called a race condition. This problem is not as severe in synchronous circuits because the outputs of the memory elements only change at each clock pulse. The interval between clock signals is designed to be long enough to allow the outputs of the memory elements to "settle" so they are not changing when the next clock comes. Therefore, the only timing problems are due to "asynchronous inputs"; inputs to the circuit from other systems which are not synchronized to the clock signal.
Asynchronous sequential circuits are typically used only in a few critical parts of otherwise synchronous systems where speed is at a premium, such as parts of microprocessors and digital signal processing circuits. The design of asynchronous logic uses different mathematical models and techniques from synchronous logic, and is an active area of research. From Wikipedia, the free encyclopedia. For the synthesizer company, see Sequential Circuits.
Main article: asynchronous circuit. Michael VLSI Design. CRC Press.